Dimension Eight Labs

ABSURDLY ACCURATE CLOCK

GPS / PPS Embedded Timing Appliance · Pico 2 / RP2350 · Serial VFD · ESP32 Time Bridge
GPS SOURCE / QUALIFICATION AUTHORITATIVE TIMING CORE NETWORK EXPORT ACTIVE GPS ANTENNA SMA · magnetic base u-blox NEO-7-class GPS UART: RMC UTC / date label PPS: precise 1 s boundary NMEA arrival does not advance the system clock. Pico associates the label with the PPS epoch. VERIFIED PHYSICAL HARDWARE RMC / PPS qualification RMC completes PPS n PPS n+1 Bench observation: completion ≈ +140 ms after preceding PPS. Qualification window: start ≥20 ms · complete ≤900 msno boundary crossing. UART0 · RMC PPS → GP2 Raspberry Pi Pico 2 / RP2350 Central timing authority RMC parser UTC + date label PPS capture minimal ISR Label / PPS qualification sequence · cadence · validity policy in normalfirmware context AUTHORITATIVE UTC PPS-driven second state GPS VALID · PPS PRESENTPPS LOCKED · UTC VALID RP2350 watchdog 4 s hardware watchdog reacquire validityafter reset DISPLAY PRESENTATION PRESENTATION / HARDWARE DRIVER Presentation state UTC / US timezonerolling seconds Display renderer display-agnosticboundary PD-2200 driver Noritake command mode UART1 TX · TTL UART MAX3232 TTL → RS-232 Alternate display driver future / alternateimplementation Posiflex PD-2200 VFD 2 × 20 character · RS-232 · Noritake mode 12:34:56 GPS+ PPS+ SAT 08 ~50% brightness · PPS-synchronized presentation RS-232 ESP32 / ESP-WROOM-32 Companion network time appliance Pico remains authority SPI Protocol v1 MODE 1 · 100 kHz · 40 bytes“ACT1” · CRC-32 Qualified TIME_SYNC Pico → ESP32 · accepted PPS boundarysoftware delayed ≤5 ms ESP32 controllerPico peripheral SPI TIME_SYNC LAN / NTP network time export CS asserted → immutable packet snapshot→ TX FIFO preload (SSE disabled) → enable SSESPI recovery/reset while deselectedTX alignment hardware verified 12 V power input / distribution 12 V → VFD regulated low-voltage rail →Pico / GPS / interface electronics Regulator topology intentionally shown generically. 12 V HARDWARE VERIFIED GPS/PPS lock · PPS-driven UTC · serial VFD · 40-byte SPI transport · CRC-valid ACT1 · TIME_SYNC phase association · ESP32 Pico-authority qualificationNOT YET ESTABLISHEDwatchdog recovery
Primary system boundary shows built/tested/documented functionality. Dashed elements indicate replaceable or future presentation-layer work; no OCXO is shown as installed.